1. Field of the Invention
This invention relates to a capacitor and a method of manufacturing the same, and in particular to a capacitor including a ferroelectric substance that is used for a semiconductor memory and a method of manufacturing the same.
2. Statement of the Problem
A ferroelectric memory which has a combination of a semiconductor and a ferroelectric substance, such as Pb(Zr1xe2x88x92xTix)O3 (hereinafter xe2x80x9cPZTxe2x80x9d) stores xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in memory by using residual polarization of the ferroelectric substance. The relation between a voltage applied to the ferroelectric capacitor and the polarization is represented as a hysteresis characteristic in FIG. 16.
For example, even when a positive bias is applied and thereafter the bias is returned to zero, the polarization does not return to zero and is held at the residual polarization +Pr. Conversely, when the bias is put into negative and thereafter the bias is returned to zero, the residual polarization xe2x88x92Pr is obtained. These states are read out and recognized as xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, which can be used as a memory by reading them. It is known to operate as a nonvolatile memory because the information is retained even when a power source is cut off. It is important that the ferroelectric capacitor and a large-scale integrated circuit (hereinafter xe2x80x9cLSIxe2x80x9d) are formed on the same substrate so that both operate with sufficient performance in this memory. Such a structure of a capacitor is disclosed in Japanese Unexamined Patent Publication No. Hei 7-111318/1995. FIG. 17 is a structural cross-sectional view thereof. In FIG. 17, the reference numeral 21 represents an underlying oxide film (BPSG) layer, the reference numeral 23 represents a lower electrode (Pt) layer, the reference numeral 24 denotes a PZT layer, the reference numeral 25 denotes a SiN layer, the reference numeral 26 represents an upper electrode (Pt) layer, the reference numeral 27 represents a TiN layer, the reference numeral 28 denotes a capacitor cover (NSG) layer, and the reference numeral 29 denotes an Al wiring layer.
In the capacitor having such a structure, the ferroelectric capacitor comprising lower electrode layer 23, dielectric layer 24 and upper electrode layer 26 is completely covered with SiN layer 25 and TiN layer 27. Although the SiN layer 25 and the TiN layer 27 are unnecessary to obtain a ferroelectric capacitor which operates normally, the reason for forming them will be explained.
Namely, in the normal LSI process, a heat treatment is carried out in a hydrogen atmosphere at about 400xc2x0 C. after formation of an Al wiring. This heat treatment is performed to reduce MOS interface levels which are generated in each step of the MOSFET fabrication used for the LSI and to reduce the variation thereof; in particular, the variation of threshold values. It is necessary to perform the heat treatment in the hydrogen atmosphere after the formation of the capacitor to improve the characteristic of the MOSFET, which is formed in the same substrate. However, a reduction reaction takes place during such a process because the ferroelectric material, such as PZT, is generally an oxide.
Consequently, oxygen deficiency occurs in the ferroelectric substance due to the heat treatment in the hydrogen. The oxygen deficiency brings about loss of ferroelectric characteristic and an increase of leakage current. As a result, the capacitance after the heat treatment is insufficient to serve in a ferroelectric capacitor.
Therefore, it is necessary in the ferroelectric capacitor to form a cover film having a barrier characteristic against the hydrogen. Such a film may be, for example, a SiN layer 25 or a TiN layer 27. With such a structure, the ferroelectric capacitor is completely covered with these films and does not deteriorate as a result of the heat treatment in the hydrogen.
Problems of the capacitor having the above structure and a method of manufacturing the same are described here. With such a structure, it is necessary to deposit SiN on the entire surface after the ferroelectric capacitor has been formed. In consideration of density and the step coverage of the film, the deposition is carried out by use of a chemical vapor deposition (hereinafter xe2x80x9cCVDxe2x80x9d) method.
Conventionally, the deterioration due to a variety of reduction processes after the formation of the capacitor has caused problems in the ferroelectric capacitor used in a semiconductor memory. To solve the problems, it is effective to form a cover film, such as SiN, having a barrier characteristic against the hydrogen. However, deterioration also occurs during the formation of the film because a gas containing hydrogen, such as SiH4 (ammonia), is used during the deposition of the SiN. SiH4 (silane) and NH4 are generally used as gases for the deposition of SiN. Furthermore, a deposition temperature of 300xc2x0 C. or more is required to obtain SiN having dense and excellent film quality.
Therefore, a reduction reaction occurs during the deposition due to the hydrogen contained in the gas, which results in deterioration of the ferroelectric characteristic. Thus, although the barrier characteristic is effective against the hydrogen after the deposition, deterioration takes place during the deposition itself because the reduction reaction occurs.
The above problem may be solved by using TiN that is deposited as the barrier film by a sputtering method. In contrast to SiN, however, TiN is electrically conductive, so it interferes with wiring material, such as an Al wiring pattern. Consequently, it is impossible to cover the entire capacitor.
Therefore, although no deterioration occurs by heat treatment after formation of the structure, deterioration takes place during the manufacturing process. Further, the fabrication process is excessively complex.
3. Solution to the Problem
It is an object of this invention to provide a structure of a capacitor and a method of manufacturing the same, in which a cover film on the capacitor has the barrier characteristic against hydrogen without causing deterioration of ferroelectric and dielectric characteristics.
According to the invention, a memory device has capacitor with a lower electrode layer, a dielectric layer and an upper electrode layer. A nonconductive hydrogen barrier layer is located on the capacitor except for a region on at least part of the upper electrode layer, while a conductive hydrogen barrier layer is formed at least partly in the region in which the nonconductive hydrogen barrier layer is not located.
Further, according to a method of manufacturing the capacitor of this invention, the lower electrode layer and the dielectric layer are successively deposited. After the lower electrode layer and the dielectric layer are selectively etched, the nonconductive hydrogen barrier layer is deposited on the above structure. After the nonconductive hydrogen barrier layer is selectively etched on the dielectric layer, a heat treatment is carried out at a temperature of 400xc2x0 C. or more, preferably in oxygen. Thereafter, the upper electrode layer and the conductive hydrogen barrier layer are successively deposited, followed by a selective etch of the upper electrode layer and the conductive hydrogen barrier layer. In this embodiment, the upper electrode layer and the conductive hydrogen barrier layer are self-aligning. The nonconductive hydrogen barrier layer and the conductive hydrogen barrier layer may be deposited using chemical vapor deposition.
According to an alternative embodiment of the method of manufacturing a capacitor of this invention, the lower electrode layer and the dielectric layer are successively deposited on a base substrate. After the lower electrode layer and the dielectric layer are selectively etched, the nonconductive hydrogen barrier layer is deposited on the above structure. After the nonconductive hydrogen barrier layer is selectively etched on the dielectric layer, a heat treatment is carried out at a temperature of 400xc2x0 C. or more, preferably in oxygen. Then, an electrode layer is deposited and selectively etched to form the upper electrode layer, and thereafter the conductive hydrogen barrier layer is deposited and selectively etched. In this embodiment, the upper electrode layer and the conductive hydrogen barrier layer are patterned separately and are, therefore, not self-aligned with each other. Rather, the conductive hydrogen barrier layer covers more than just the upper electrode.
In an embodiment of the invention, an underlying electrically nonconductive hydrogen barrier is located below the lower electrode layer on the entire surface of the base substrate on which the capacitor is formed. In another embodiment of the invention, an underlying conductive hydrogen barrier layer is located below the lower electrode layer and is etched and PATTERNED together with the lower electrode layer. The base substrate may be a silicon substrate. According to the invention, a base insulating film may be located on the substrate. The underlying conductive hydrogen barrier layer or the underlying nonconductive hydrogen barrier layer may be located directly on a substrate or on an insulating film that is on the substrate. An integrated circuit may also be located on the substrate.
When the nonconductive hydrogen barrier layer is etched, an opening corresponding to the upper electrode is formed. The heat treatment in oxygen, before deposition of the upper electrode layer and the conductive hydrogen barrier layer, serves to recover the deterioration of properties of the dielectric layer caused by reduction reactions in prior manufacturing processes.
Furthermore, after deposition of the upper electrode layer and the conductive hydrogen barrier layer, the opening through the nonconductive hydrogen barrier is completely covered with the conductive hydrogen barrier layer. Consequently, the above structure possesses a barrier characteristic against the hydrogen process after formation of the capacitor, resulting in no deterioration in the dielectric layer during subsequent reducing processes.
A feature of the invention is that the dielectric layer may contain a ferroelectric material or a high dielectric-constant material. The ferroelectric material is a ferroelectric metal oxide, such as Pb(Zr,Ti)O3 and SrBi2Ta2O9. The high dielectric-constant material is a nonferroelectric dielectric metal oxide, such as (Sr,Ba)TiO3.
The nonconductive hydrogen barrier layers may comprise SiN. It is a feature of the invention that a SiN film or other nonconductive hydrogen barrier layer may be deposited using a chemical vapor deposition method. The conductive hydrogen barrier layers typically comprise a metal nitride. Such metal nitrides include TiN and AlN.
The conductive hydrogen barrier layer may be located directly on the upper electrode layer. Also, a buffer film may be located on the upper electrode, with the conductive hydrogen barrier layer located on the buffer film.
After the upper electrode and the conductive hydrogen barrier layer are patterned into the predetermined shape, typically an insulating capacitor cover layer is deposited on the capacitor, a contact hole is formed by the etching, and an Al wiring pattern is formed. The capacitor cover layer may be formed using a chemical vapor deposition method.
Usually after the insulating film and wiring layer are formed, a hydrogen heat treatment may be conducted, typically at a temperature of 300xc2x0 C. or higher.
Therefore, the heat treatment in the hydrogen can be carried out to improve the characteristic of the MOSFET. Consequently, a memory having an excellent characteristic can be obtained with an excellent yield.